1. Field of the Invention:
The present invention relates to test apparatus for semiconductor devices and, more particularly, to test apparatus for testing the operational reliability of mixed-signal semiconductor devices.
2. Description of the Related Art:
Large scale integration (LSI) devices refer to electronic circuits that have many components on a single chip. A system LSI may include a plurality of circuits having different functions, such as a central processing unit, a memory, an integrated circuit for processing video and audio data, and an integrated circuit for communication. A System On Chip (SOC) is an example of the system LSI. A SOC may use a mixture of analog and digital signals. A test apparatus for testing the reliability of an SOC semiconductor device may require testing of both digital and analog signals.
FIG. 1 is a schematic view of one example of a conventional test apparatus for a mixed-signal semiconductor device. FIG. 2 is a block diagram of the device shown in FIG. 1. It is noted that the test apparatus shown in FIGS. 1 and 2 is just one example of a conventional test apparatus.
As shown in FIGS. 1 and 2, the test apparatus comprises a test controller 310, a test head 320, a performance board 360, a device under test (DUT) 350, and a test fixture 370.
The test head 320 includes a combination of the same-type of tester modules and of different-type tester modules. For example, a test head may include a high speed signal tester module and a low speed signal tester module.
Each tester module includes a plurality of event tester boards 321 and 323. The event tester boards 321 and 323 include a plurality of event testers 331 corresponding to tester pins. The event tester boards 321 perform analog processing and the event tester boards 323 perform a digital processing.
The test controller 310 may be a host computer. It controls a plurality of event tester boards 321 and 323 through a system bus 315. For example, as shown six event tester boards 321 and 323 are installed in a single tester module. The test apparatus may include two or more tester modules.
The analog processing event tester board 321 applies a test pattern to the DUT 350 and tests a response signal from the DUT 350. An option circuit 341 connects the event tester board to the analog pins on the DUT 350. The option circuit 341 includes a D/A converter, an A/D converter and a filter.
The event tester boards 321 and 323 include event testers 331 for thirty two-channels, an interface 332, a processor 333 and a memory 334. Each event tester 331 has the same inner structure as the tester pins. The event tester 331 may include an event memory 335, an event operation unit 336, a driver/comparator 337 and a capture memory 338. The event memory 335 memorizes an event data for generating the test pattern. The event operation unit 336 generates the test pattern based on the event data. The driver/comparator 337 compares an output signal and an expected signal from the DUT 350. The capture memory 338 stores the test result. The A/D converter in the option circuit 341 converts an analog signal to a digital signal.
The interface 332 and processor 333 are connected to the tester controller 310 through the system bus 315. The interface 332 transmits data from the tester controller 315 to a register on the event tester board 321, so as to assign the event testers 331 to input/output pins of the DUT 350.
The processor 333 controls the operations occurring on the event tester boards 321 and 323, including generating the test pattern, evaluating the output signal from the DUT 350, and detecting faulty data.
The test head 320 provides a plurality of tester modules depending on the number of pins in the test fixture 370 and the type and the number of pins on the DUT 350. The test fixture 370 may include a plurality of elastic connectors such as pogo pins. The test fixture 370 electrically and mechanically connects the event tester boards 321 and 323 and the performance board 360. The DUT 350 is inserted in a test socket of the performance board 360, which establishes an electrical communication with the test apparatus 300.
A test pattern is generated by the event tester boards 321 and 323 and is applied to pins of the DUT 350 through the performance board 360. In response to the test pattern, the output signal from the DUT 350 is transmitted to the event tester boards 321 and 323 through the performance board 360. The output signal is compared with an expected signal. The success or failure of the DUT 350 is then determined. Each tester module includes a connector to the test fixture 370.
A conventional test apparatus for a mixed-signal semiconductor device includes an event tester board having a video signal source/digitizer function for testing a low frequency analog signal such as an audio signal and a high frequency analog signal such as a video signal. Therefore, conventional test apparatus may simultaneously test an A/D converter circuit, a logic circuit and a D/A converter circuit of a mixed-signal semiconductor device.
The number of DUTs is determined by the number of analog event tester boards. As the number of the analog event tester boards increases, the number of the DUT may increase, thereby allowing a parallel test. A test apparatus for a mixed-signal semiconductor device may employ two sets of analog event tester boards, realizing two-parallel test.
However, increasing the number of analog event tester boards may result in an increase in production cost. When considering the ratio of performance to production cost, it may be inefficient to increase the number of event tester boards.